Central processing units (CPUs) are generally mounted with a cache memory for temporarily storing data. A cache memory is a memory capable of high-speed operation which copies and stores part of the content of data in a low-speed main memory. When data required by the CPU is stored in the cache memory, the CPU can perform arithmetic processing at high speed.
Here, a state where data required by the CPU is stored in the cache memory is called a cache hit, and a state where the data is not stored in the cache memory is called a cache miss. In the case of a cache miss, the CPU fetches the required data from the low-speed main memory.
Typical structures of a cache memory are a fully associative structure, a direct mapped structure, a set associative structure, and the like.
An n-way set associative cache memory uses n memory sets. Each memory set includes one comparison circuit and m lines which are assigned to lower-order bits of an address of a main memory. Each line includes a tag field for storing higher-order bits of the address of the main memory and a data field for storing data corresponding to the address. Each line is also referred to as a unit of data control in the memory set.
In addition, a control portion for controlling the operation of the cache memory is provided in the cache memory. The control portion can select a specific line of a specific set in the cache memory and read data stored in the line or store data in the line.
A method for storing a piece of data, which is specified by an address, in the cache memory is described. The control portion refers to lower-order bits of the address, and selects one of the lines (n lines in total) corresponding to the lower-order bits in the respective memory sets, as a candidate storage location.
In the case where a least recently used (LRU) mode is used as a rewriting algorithm for the cache memory, the line which has not been used for the longest time of the n lines is determined as the storage location and data in the line is overwritten with the piece of data. Specifically, higher-order bits of the address are stored in the tag field, and a copy of data in the main memory is stored in the data field.
Next, a method by which the cache memory outputs data is described. When the CPU fetches data specified by an address from the control portion provided in the cache memory, the control portion selects the line corresponding to the lower-order bits of the address in each of the n memory sets. Then, the comparison circuit provided in each memory set compares the higher-order bits of the address with the higher-order bits stored in the tag field, and outputs the data stored in the data field of that line to the CPU when the higher-order bits match each other (a cache hit). On the other hand, when the higher-order bits of the address do not match the higher-order bits stored in the tag field in all the n lines (a cache miss), the CPU fetches data from the main memory.
In recent years, a metal oxide having semiconductor characteristics, which is called an oxide semiconductor exhibiting high mobility and uniform element characteristics, has attracted attention as a material of a transistor. Metal oxides are used for a variety of applications. For example, indium oxide is used as a material of a pixel electrode in a liquid crystal display device. Examples of such metal oxides showing semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, and zinc oxide, and transistors in each of which a channel is formed using such a metal oxide showing semiconductor characteristics have been known (Patent Documents 1 and 2).